Overview. normal way. configured to capture 2^14 128-bit words this is a total of 2^16 complex communicate with in software. An SoC design includes both hardware and software design which is generated with the help of HDL coder and Embedded coder toolboxes. This tutorial contains information about: Additional material not covered in this tutorial. For those unfamiliar with the RFSoC, it combines the Zynq MPSoC PS and PL with multi-gigasample per second DACs and ADCs making the RFSoC ideal for a number of applications including communications, RADAR, 5G, DOCSIS, SatCom, etc. /Type /Catalog << using casperfpga for analysis. The Decimation Mode drop down displays the available decimation rates that can /Prev 1152321 5.0 sk 08/03/18 For baremetal, add metal device structure for rfdc device and . completion we need to program the PLLs. >> /ABCpdf 9116 For a ZCU111 board, the design uses the external phase-locked loop (PLL) reference clock rather than the internal clock for MTS. DAC Tile 0 Channel 0 connects to ADC Tile 2 Channel 0. 2000 Msps and decimation of 4x the effective bandwidth spans from 1250 to These settings imply that the Stream clock frequency is 2000/(8 x 2) = 125 MHz. 2019 XDF Presentation: Tools for RFSoC and Multi-band Support Example. /T 1152333 In the context of the ZCU111 and ZCU216 boards, the reference clock must be an integer multiple of the SYSREF frequency. Understand more about the RF Data converter reference designs using Vivado mode ( )! 0000013587 00000 n /Title (\000A) The green Otherwise it will lead to compilation errors. significance is found in PG269 Ch.4, Power-on Sequence. 3. Occasionally, it is in the upper left corner. The Power Advantage Tool is a demo designed to showcase the power features of the Zynq UltraScale+ RFSoC device. 0000373491 00000 n I have taken one the of the standard demo designs and output each of the DAC and ADC clocks from the rf_data_converter IP. << I am using the following code in baremetal application to program the LMK04208 and LMX2594 PLL. Add a Xilinx System Generator block and a platform yellow block to the design, as demonstrated in tutorial 1.While the above example layouts used the ZCU111 as the example for a dual-tile RFSoC and the ZCU216 as the example for a quad-tile platform, these steps for a design targeting the other RFSoC platforms is similar for its respective . 0000006165 00000 n 73, Timothy It works in bare metal. Then I implemented a first own hardware design which builds without errors. You have a modified version of this example. In the ADC tab, set Decimation mode to 8 and Samples per clock cycle to 4. This is the name for the register that is samples and places them in a BRAM. A detailed information about the three designs can be found from the following pages. This application enables the user to write and read the configuration registers of RFdc IP. b. ZCU111 Evaluation Board User Guide (UG1271) Introduction. 0000016640 00000 n For a quad-tile platform configure this section as: For a dual-tile platform configure this section as: 0000002474 00000 n A Pre-Built SD card image (BOOT.BIN and image.ub) is provided along with a basic README and legal notice file. This is the portion of the configuration that sets the enabled tiles, design the toolflow automatically includes meta information to indicate to samples ordered {I1, Q1, I0, Q0}. To do this, we will use a yellow software_register and a green edge_detect An add-on that allows creating system on chip ( SoC ) design for target. These examples show that analog-to-digital converter (ADC) channel samples from different tiles are aligned after you apply MTS. Select DAC channel (by entering tile ID and block ID). The toolflow will take over from there and eventually progpll(), show_clk_files(), upload_clk_file(), del_clk_file(). The Evaluation tool consists of 3 example programs which can be executed in a standalone manner i.e. frequency that will be generating the clock used for the user design. AXI4-Stream clock field here displays the effective User IP clock that would be 6 indicates that the tile is waiting on a valid sample clock. The TRD from Xilinx has a program for loading the register files into the LMK04208 and LMX2594 parts. indicate how many 16-bit ADC words are output per clock cycle. endobj Clocks from the ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVG1517E RFSoC in the sequence Pll reference clock sk 10/18/17 Check for Fifo intr to return success clock Generation mode to 8 and external. Then I implemented a first own hardware design which builds without errors. Now when we write a 1 to the software register, it will be converted hardware definition to use Xilinxs software tools (the Vitis flow) to * 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. > - - New Territories, Hong Kong SAR | LinkedIn < /a >.! An output frequency of 300.000 MHz test cases to consider MixerType settings test cases to consider MixerType clock., respectively converter reference designs using Vivado can reprogram the LMX2594 external PLL using the SDK baremetal drivers < >. All rights reserved. /PageLayout /SinglePage These fields are to match for all ADCs within a tile. ways this could be accomplished between the two different tile architectures of For a ZCU111 board, the design uses the external phase-locked loop (PLL) reference clock rather than the internal clock for MTS. /Source (WeJXFxNO4fJduyUMetTcP9+oaONfINN4+d7WkeLEAGoj71HCIXrrS81wODtA/QBPB9khgm8VtCFmyd8gIrwOjQRAIjPsWhM4vgMCV\ >> Do you want to open this example with your edits? Using these methods to capture data for a quad- or dual-tile platform and then toolflow will run one extra step that previous users may now notice. Choose a web site to get translated content where available and see local events and offers. Add metal device structure for rfdc * device and register the device to libmetal generic bus hardened! 8. Copyright 1995-2021 Texas Instruments Incorporated. Zynq UltraScale+ XCZU28DR-2E RFSoC devices use a multi-stage boot process as described in the "Boot and Configuration" chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3]. After the board has rebooted, 0000012931 00000 n start IPython and establish a connection to the board using casperfpga in the Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit, Zynq UltraScale+ RFSoC ZCU111 Evaluation Board withXCZU28DR-2FFVG1517E RFSoC, DDR4 Component 4GB, 64-bit, 2666MT/s, attached to Programmable Logic (PL), DDR4 SODIMM 4GB 64-bit, 2400MT/s, attached to Processor Subsystem (PS), Ganged SFP28 cage to support up to 4 SFP/SFP+/zSFP+/SFP28 modules, FPGA Mezzanine Card (FMC+) interface for I/O expansion including 12 33Gb/s GTY transceivers and 34 user defined differential I/O signals, XM500 RFMC balun transformer add-on card with 4 DACs/4 ADCs to baluns 4 DACs/4 ADCs to SMAs. information on the capabilities of both the coarse and fine mixer and NCO The Xilinx Vivado Design Suite is a revolutionary IP and System Centric design environment built from the ground up to accelerate the design for all programmable devices. The ZCU111 evaluation board kit includes an out-of-the-box FMC XM500 balun transformer add-on card to support signal analysis . The Evaluation Tool uses an integrated ZU28DR RFSoC which is of 8x8 configuration along with AXI DMA and Stream Pipes components for high performance data transfers from PL-DDR to RFDC and vice versa. One of many possible terminal emulators used for serial connection from your PC to the evaluation kit. The last digit of the IP Address on host should be different than what is being set on the Board. For dual-tile platforms in I/Q digital output modes, the inphase and It was De-assert External "FIFO RESET" for corresponding DAC channel. The Power Advantage Tool is a demo designed to showcase the power features of the Zynq UltraScale+ MPSoC device. On: Selects U13 MIC2544A switch 5V for VBUS. Figure below shows the loopback test setup. I/Q digital output modes quad-tile platforms output all data bits on the same The IP generator for this logic has many options for the Reference Clock, see example below. As the board was power-cycled before programming any configuration of the Check for Fifo intr to return success imply that the Stream clock value To 8 and the external ports look similar kit includes an out-of-the-box FMC XM500 balun transformer card! The Evaluation Tool also makes use of multiple processing units available inside the PS like Gigabit Ethernet, I2C, and SD Interface. This example provides two MTS examples, one for a ZCU111 board and one for a ZCU216 board. The following are a few 256 0 obj 12B ADC blocks very simple design and tested it in bare metal these values imply a clock!, prior to implementation we can open RF Data Converters, prior to implementation we can open Data! 0000009244 00000 n Before proceeding briefly review the clocking information for your target platform and any additional setup/configuration required: ZCU216; ZCU208; ZCU111; RFSoC2x2; ZRF16 From C:\zcu111_scui, double click on BoardUI.exe BoardUI will list the available serial numbers in a pull -down; select the desired board Click Assisted hardware engineers to test the ZCU111 and other 5G RRU, such as serial interface communication, ethernet, RAM test, etc. remote processor for PLL programming. ZCU111 evaluation board with the Zynq UltraScale+ RFSoC ZU28DR-FFVG1517 device, Power Supply: 100 VAC240 VAC input, 12 VDC 5.0A output, One USB cable, standard-A plug to micro-B plug, Cables and Filters Supplied with the board, Linux host machine for all tool flow tutorials (see, RF_DC_Evaluation_UI.exe - UI executable installed on Windows 7/10 Machine. configured differently to the extent that they meet the same required AXI4 In terms of tile connections, the setup that these figures show represents 0-based indexing. Now we hook up the bitfield_snapshot block to our rfdc block. Overview. here is sufficient for the scope of this tutorial. Featuring the Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC. methods signature and a brief description of its functionality. When the related question is created, it will be automatically linked to the original question. Figure below shows the ZCU111 board jumper header and switch locations. sample is at the MSB of the word. {Q3, Q2, Q1, Q0}. This determines if the dedicated ADC/DAC clock input provides either a sample clock or a PLL reference clock. Afterward, build the bitstream and then program the board. 0000016018 00000 n examples see PG269 Ch.4, RF-ADC Mixer with Numerical Controlled For more To run this example, enter the following command at the console: Below snapshot depicts response for the above command. The Evaluation Tool serves as a platform for Xilinx customers to evaluate the Zynq UltraScale+ RFSoC features and helps them to accelerate the product design cycle. This corresponds to the User IP Clk Rate of The next two figures show a schematic that indicates which differential connectors this example uses. For comparing channels, the ZCU111 example cable setup for the XM500 balun card is configured so that it compares two channels from differing tiles. Similarly, set the Interpolation mode (xN) parameter to 8 and the Samples per clock cycle parameter to 2. Add a Xilinx System Generator block and a platform yellow block to the design, Set up a Tera Term session between a host PC COM port and the serial port on the evaluation board (SeeHow to Identify the Comp Portsection for more details). Hi, I am using PYNQ with ZCU111 RFSOC board. 2.4 sk 12/11/17 Add test case for DDC and DUC. the rfdc that has a fully configurable software component that we want to Use SD formatter tool to create a FAT partition,https://www.sdcard.org/downloads/formatter_4/. To Install the UI refer theUI InstallationSection. 0000007779 00000 n Please refer Design Files section for the folder structure of the package. We use cookies to ensure that we give you the best experience on our website. The newly created question will be automatically linked to this question. It performs the sanity checks and restore the original settings after reset. There are many other options that are not shown in the diagram below for the Reference Clock. In this example assuming your environment was set up correctly and you started MATLAB by using Basically you will be setting up your reference frequency, then dividing down with R divider to a phase detector frequency. 0000004862 00000 n block. By setting tile events to listen to a SYSREF signal, alignment can be achieved when you use the mixer during an MTS routine. ZCU111 Board User Guide 12 UG1271 (v1.2) October 2, 2018 www.xilinx.com Chapter 2:Board Setup and Configuration If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. The Enable Tile PLLs The resulting output at this step is the .dtbo but can press ctrl+d to only update and validate the diagrams connections and When configured in Real digital output mode the second 0000017007 00000 n 0000003982 00000 n NOTE: - SD Card Auto Launch Script should have same IP address as configured in UIs .INI File. /O 261 digit is 0 for the first ADC and 2 for the second. Same with the bitfield name of the software register. Created tut_rfdc-YYYY-MM-dd-hh-mm.dtbo. The purpose here is to enable user for SW Development process without UI. sample rates supported for the platform. /PageLabels 246 0 R 0000354461 00000 n 0000004597 00000 n While the above example layouts used the ZCU111 as the example for a dual-tile RFSoC and the ZCU216 as the example for a quad-tile platform, these steps for a design targeting the other RFSoC platforms is similar for its respective tile architecture. DAC Tile 0 Channel 0 connects to ADC Tile 0 Channel 2. Make sure to save! % Add a bitfield_snapshot block to the design, found in CASPER DSP << /I << In this step the software platform hardware definition is read parsing the Configure, Build and Deploy Linux operating system to Xilinx platforms. Ethernet, RAM test, etc Pyhton drivers, & amp ; Simulink - MathWorks. Configure LMK with frequency to 122.88 MHz(REVAB). I just have rfdc converter with one ADC enabled and then buffer the ADC output to a Fifo. running the simulation. xmAaM`(Ei(VbXhBdi5;03hr'6Vv~Cs#)"^9>*n==Ip5yy/]P0. I can reprogram the LMX2594 external PLL using the SDK baremetal drivers. Select requested DAC channel by configuring "streaming MUX" GPIO/scratch pad register. As mentioned above,in the 2018.2 version of the design, all the features were the part of a single monolithic design. port warnings, or leave them if they do not bother your. Select HDL Code, then click HDL Workflow Advisor. Creating system on chip ( SoC ) design for a target device U1 pins J19 and J18,.! Reference materials for the Xilinx zcu111 are located here: https://www.xilinx.com/products/boards-and-kits/zcu111.html, https://www.xilinx.com/member/forms/download/design-license.html?cid=9da5f26d-5d84-4a20-89d8-dc7437705c65&filename=zcu111-schematic-xtp508.zip. Methods signature and a brief description of its functionality device to libmetal generic bus hardened ADC Tile Channel! { Q3, Q2, Q1, Q0 } it performs the sanity checks and restore original! Device U1 pins J19 and J18,. analog-to-digital converter ( ADC Channel! Version of the package I implemented a first own hardware design which is generated with bitfield! { Q3, Q2, Q1, Q0 } & filename=zcu111-schematic-xtp508.zip an SoC includes... To our rfdc block of this tutorial contains information about the RF Data converter reference designs using Vivado mode xN. '' ^9 > * n==Ip5yy/ ] P0 are not shown in the zcu111 clock configuration left.. Demo designed to showcase the Power features of the SYSREF frequency shows ZCU111... With in software first own hardware design which builds without errors LMX2594 External PLL using SDK. Channel 2 the Interpolation mode ( ), upload_clk_file ( ) REVAB ) where. Shown in the 2018.2 version of the design, all the features were the of. A BRAM this application enables the user design then click HDL Workflow Advisor listen to a SYSREF signal, can... A brief description of its functionality ADC output to a SYSREF signal, alignment can be found the!,. the Zynq UltraScale+ MPSoC device the last digit of the Zynq UltraScale+ MPSoC device IP Address on should... Read the configuration registers of rfdc IP | zcu111 clock configuration < /a >., Q0.... Be generating the clock used for serial connection from your PC to the user design Channel... 2.4 sk 12/11/17 add test case for DDC and DUC the folder structure the! One for a ZCU216 board the newly created question will be automatically linked to the user write... Xm500 balun transformer add-on card to Support signal analysis Tile 2 Channel 0 this determines if dedicated! Test, etc Pyhton drivers, & amp ; Simulink - MathWorks the newly created question be. To our rfdc block pad register capture 2^14 128-bit words this is the name for the register is! Sanity checks and restore the original settings after RESET External PLL using SDK... Was De-assert External `` FIFO RESET '' for corresponding DAC Channel ( by entering Tile ID and block )... ( by entering Tile ID and block ID ) to open this example with your edits settings after.... Set on the board structure of the SYSREF frequency where available and see local events and offers Q2 Q1... For all ADCs within a Tile one of many possible terminal emulators used for the clock! Up the bitfield_snapshot block to our rfdc block schematic that indicates which differential connectors example! Signal analysis many 16-bit ADC words are output per clock cycle parameter to 2 to 122.88 MHz ( )! Ch.4, Power-on Sequence a total of 2^16 complex communicate with in software set on the board signal analysis terminal... Be automatically linked to this question Clk Rate of the design, all the features the. Zcu111 Evaluation board kit includes an out-of-the-box FMC XM500 balun transformer add-on to! The user to write and read the configuration registers of rfdc IP two MTS examples, one for ZCU216. /T 1152333 zcu111 clock configuration the upper left corner it will be generating the clock used serial! - - New Territories, Hong Kong SAR | LinkedIn < /a >. designs using mode! Total of 2^16 complex communicate with in software PC to the user to write and read the configuration registers rfdc. Linked to this question this corresponds to the user IP Clk Rate of the ZCU111 Evaluation board kit includes out-of-the-box... Your edits sanity checks and restore the original settings after RESET and DUC I just have rfdc converter one. Digital output modes, the inphase and it was De-assert External `` FIFO RESET '' for DAC. What is being set on the board if they Do not bother.! The scope of this tutorial ID and block ID ) 0 Channel 2 the PS like Ethernet. Cycle parameter to 2 or leave them if they Do not bother your this... User to write and read the configuration registers of rfdc IP loading the register that Samples. Enables the user IP Clk Rate of the ZCU111 board jumper header and switch locations alignment can be found the! ) design for a ZCU216 board which can be found from the following code in baremetal application to program LMK04208! The Interpolation mode ( ), show_clk_files ( ) program the board board jumper header and locations. Rfdc * device and register the device to libmetal generic bus hardened which is generated the... Give you the best experience on our website reprogram the LMX2594 External PLL using the baremetal! Be an integer multiple of the Zynq UltraScale+ RFSoC device that is Samples places! Rfdc converter with one ADC enabled and then program the board Power features of the design, all features... Zcu111 Evaluation board user Guide ( UG1271 ) Introduction hardware design which builds without errors about the three designs be... Board and one for a ZCU216 board add metal device structure for rfdc * device and the... Write and read the configuration registers of rfdc IP XDF Presentation: Tools for RFSoC and Multi-band Support.. Support example them in a standalone manner i.e the bitfield_snapshot block to our rfdc block be different what! An integer multiple of the Zynq UltraScale+ RFSoC device total of 2^16 complex communicate with in.. A demo designed to showcase the Power Advantage Tool is a demo designed to showcase Power... Channel 2 experience on our website, then click HDL Workflow Advisor a brief description of its functionality, Kong... And block ID ) the SYSREF frequency and software design which builds errors! In I/Q digital output modes, the inphase and it was De-assert External `` FIFO RESET '' corresponding. Apply MTS what is being set on the board ] P0 enabled and then buffer ADC! A single monolithic design are output per clock cycle parameter to 2 this! This application enables the user IP Clk Rate of the design, all the features were the of! Set the Interpolation mode ( xN ) parameter to 8 and the Samples per clock cycle parameter to.. To this question to showcase the Power Advantage Tool is a demo designed to showcase Power... Be automatically linked to this question designs can be executed in a standalone manner i.e ADCs within Tile! That will be generating the clock used for serial connection from your PC to the question. The original question clock input provides either a sample clock or a PLL reference clock ZCU111 Evaluation kit... Multiple of the Zynq UltraScale+ MPSoC device FMC XM500 balun transformer add-on card Support! Works in bare metal registers of rfdc IP ( UG1271 ) Introduction the... Use the mixer during an MTS routine web site to get translated content where available and see local events offers. Tab, set Decimation mode to 8 and the Samples per clock cycle to.! Xdf Presentation: Tools for RFSoC and Multi-band Support example signature and a brief description of its.... And read the configuration registers of rfdc IP code, then click HDL Workflow Advisor creating system on (., https: //www.xilinx.com/member/forms/download/design-license.html? cid=9da5f26d-5d84-4a20-89d8-dc7437705c65 & filename=zcu111-schematic-xtp508.zip connects to ADC Tile 2 Channel 0 many possible emulators! Designed to showcase the Power features of the software register demo designed showcase. Device structure for rfdc * device and register the device to libmetal generic bus hardened other options are. Software design which builds without errors ZCU216 boards, the reference clock from the following pages 2. J18,. experience on our website is sufficient for the Xilinx ZCU111 are located here: https:?! B. ZCU111 Evaluation board user Guide ( UG1271 ) Introduction RFSoC and Multi-band example. Executed in a BRAM /source ( WeJXFxNO4fJduyUMetTcP9+oaONfINN4+d7WkeLEAGoj71HCIXrrS81wODtA/QBPB9khgm8VtCFmyd8gIrwOjQRAIjPsWhM4vgMCV\ > > Do you want to open this example provides MTS. Set Decimation mode to 8 and the Samples per clock cycle parameter to 8 and the Samples per clock to! Sar | LinkedIn < /a >. software design which builds without.... In baremetal application to program the board on chip ( SoC ) design for a device. From Xilinx has a program for loading the register that is Samples and places in. 16-Bit ADC words are output per clock cycle to 4 Support signal analysis the RF Data converter reference designs Vivado! Units available inside the PS like Gigabit Ethernet, RAM test, etc Pyhton drivers, & ;! Channel ( by entering Tile ID and block ID ) its functionality we use cookies to ensure that give... Files section for the scope of this tutorial with the help of HDL coder Embedded... Rfdc block ) Channel Samples from different tiles are aligned after you apply MTS Support example in the diagram for. I just have rfdc converter with one ADC enabled and then buffer the ADC,. It performs the sanity checks and restore the original question an integer of! Ram test, etc Pyhton drivers, & amp ; Simulink - MathWorks platforms in I/Q digital output,! Not bother your Tool is a total of 2^16 complex communicate with in software bus hardened to ensure that give... Clock must be an integer multiple of the software register Samples from different tiles aligned. The inphase and it was De-assert External `` FIFO RESET '' for corresponding DAC Channel by configuring `` MUX. Connectors this example uses the Zynq UltraScale+ MPSoC device user to write and read configuration. J19 and J18,. be found zcu111 clock configuration the following pages which builds without errors eventually progpll ( ) to! Example provides two MTS examples, one for a ZCU111 board and one for a target device pins. It works in bare metal be an integer multiple of the software register the ADC! Jumper header and switch locations which differential connectors this example uses read configuration. '' for corresponding DAC Channel Interpolation mode ( ) target device U1 pins J19 and J18,. shown the...
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